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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
POWER GOOD FAST-TRANSIENT RESPONSE 7.5-A LOW-DROPOUT VOLTAGE REGULATORS
FEATURES
* * * * * * * * * 7.5-A Low-Dropout Voltage Regulator Available in 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed-Output and Adjustable Versions Open Drain Power-Good (PG) Status Output (Fixed Options Only) Dropout Voltage Typically 400 mV at 7.5 A (TPS75933) Low 125 A Typical Quiescent Current Fast Transient Response 3% Tolerance Over Specified Conditions for Fixed-Output Versions Available in 5-Pin TO-220 and TO-263 Surface-Mount Packages Thermal Shutdown Protection
EN IN GND OUTPUT FB/PG TO-220 (KC) PACKAGE (TOP VIEW) 1 2 3 4 5 TO-263 (KTT) PACKAGE (TOP VIEW) EN IN GND OUTPUT FB/PG 1 2 3 4 5
DESCRIPTION
The TPS759xx family of 7.5-A low dropout (LDO) regulators contains four fixed voltage option regulators with integrated power-good (PG) and an adjustable voltage option regulator. These devices are capable of supplying 7.5 A of output current with a dropout of 400 mV (TPS75933). Therefore, the devices are capable of performing a 3.3-V to 2.5-V conversion. Quiescent current is 125 A at full load and drops below 10 A when the devices are disabled. The TPS759xx is designed to have fast transient response for large load current changes.
TPS75933
600 IO = 7.5 A 500 VDO - Dropout Voltage - mV
VO - Change in Output Voltage - mV
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
TPS75915
LOAD TRANSIENT RESPONSE
200 100 0 -100 -200 10 5 I O - Output Current - A VO = 1.5 V Co = 100 F di + 1 A ms dt
400
300
200
100
0
0 -40 -25 -10 -5
20 35
50 65
80 95 110 125
0
20
40
60
TJ - Junction Temperature - C
80 100 120 140 160 180 200 t - Time - s
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000-2004, Texas Instruments Incorporated
TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 400 mV at an output current of 7.5 A for the TPS75933) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 125 A over the full range of output current, 1 mA to 7.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when EN is connected to a low-level voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 A at TJ = 25C. The power-good terminal (PG) is an active low, open drain output, which can be used to implement a power-on reset or a low-battery indicator. The TPS759xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.22 V to 5 V). Output voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The TPS759xx family is available in a 5-pin TO-220 (KC) and TO-263 (KTT) packages. AVAILABLE OPTIONS
TJ OUTPUT VOLTAGE (TYP) 3.3 V 2.5 V -40C to 125C 1.8 V 1.5 V Adjustable 1.22 V to 5 V (1) TO-220 (KC) TPS75933KC TPS75925KC TPS75918KC TPS75915KC TPS75901KC TO-263 (KTT) (1) TPS75933KTT TPS75925KTT TPS75918KTT TPS75915KTT TPS75901KTT
The TPS75901 is programmable using an external resistor divider (see application information). Add T for KTT devices in 50-piece reel. Add R for KTT devices in 500-piece reel.
2 5
VI
IN
PG
PG
OUT 1 F 1 EN
4
VO Co(1) 47 F
+ GND 3
(1) See application information section for capacitor selection details.
Figure 1. Typical Application Configuration (For Fixed Output Options) Terminal Functions (TPS759xx)
TERMINAL NAME EN FB/PG GND IN OUTPUT NO. 1 5 3 2 4 I O I/O I I/O Enable input Feedback input voltage for adjustable device/PG output for fixed options Regulator ground Input voltage Regulated output voltage DESCRIPTION
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
FUNCTIONAL BLOCK DIAGRAM - ADJUSTABLE VERSION
VIN UVLO Current Sense ILIM GND EN _ SHUTDOWN R1 + FB UVLO R2 VOUT
Thermal Shutdown Vref = 1.22 V
External to the Device
VIN
Bandgap Reference
FUNCTIONAL BLOCK DIAGRAM - FIXED VERSION
VIN UVLO Current Sense ILIM _ GND UVLO EN R2 SHUTDOWN R1 + VOUT
Thermal Shutdown Vref = 1.22 V VIN Bandgap Reference Falling Edge Delay PG
3
TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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TPS759xx PG TIMING DIAGRAM
VIN1 VUVLO
VUVLO
t VOUT Threshold Voltage VIT- (see Note A) t PG Output VIT+(see Note A)
t
NOTE A: VIT -Trip voltage is typically 9% lower than the output voltage (91%VO) VIT- to VIT+ is the hysteresis voltage.
DETAILED DESCRIPTION
The TPS759xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an adjustable regulator, the TPS75901 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.
PIN FUNCTIONS
Enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. Power-Good (PG) The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status of VO (output of the LDO). When VOreaches approximately 91% of the regulated voltage, PG will go to a low impedance state. It will go to a high-impedance state when VO falls below 91% (i.e., over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. Feedback (FB) FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and VO to filter noise is not recommended because it may cause the regulator to oscillate.
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
Input Voltage (IN) The VIN terminal is an input to the regulator. Output Voltage (OUTPUT) The VOUTPUT terminal is an output to the regulator.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted) (1)
TPS759XX Input voltage range (2) VI -0.3 V to 6 V -0.3 V to 6 V 6V Internally limited See Dissipation Rating Table VO (OUTPUT, FB) TJ Tstg HBM CDM (1) (2) 5.5 V -40C to 150C -65C to 150C 2 kV 500 V Voltage range at EN Maximum PG voltage (TPS759xx) Peak output current Continuous total power dissipation Output voltage Operating junction temperature range Storage temperature range ESD rating
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE
PACKAGE TO-220 TO-263 (1) (2) (3) RJC (C/W) 2 2 RJA (C/W) (1) 58.7 (2) 38.7 (3)
For both packages, the RJAvalues were computed using JEDEC high K board (2S2P) with 1 ounce internal copper plane and ground plane. There was no air flow across the packages. RJA was computed assuming a vertical, free standing TO-220 package with pins soldered to the board. There is no heatsink attached to the package. RJA was computed assuming a horizontally mounted TO-263 package with pins soldered to the board. There is no copper pad underneath the package.
RECOMMENDED OPERATING CONDITIONS
MIN VI (1) VO IO TJ (1) Input voltage Output voltage range Output current Operating virtual junction temperature 2.8 1.22 0 -40 MAX 5.5 5 7.5 125 UNIT V V A C
load).
To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min)= VO(max)+ VDO(max
5
TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (TJ = -40C to 125C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 100 F (unless otherwise noted)
PARAMETER TEST CONDITIONS 1.22 V VO 5.5 V, TJ = 25C Adjustable voltage 1.22 V VO 5.5 V 1.22 V VO 5.5 V, TJ = 0 to 125C (2) TJ = 25C, 2.8 V < VI < 5.5 V 2.8 V VI 5.5 V TJ = 25C, 2.8 V < VI < 5.5 V 2.8 V VI 5.5 V TJ = 25C, 3.5 V < VI < 5.5 V 3.5 V VI 5.5 V TJ = 25C, 4.3 V < VI < 5.5 V 4.3 V VI 5.5 V TJ = 25C VO + 1 V VI 5.5 V, TJ = 25C VO + 1 V VI < 5.5 V 0.35 TPS75915 BW = 300 Hz to 50 kHz, TJ = 25C, VI = 2.8 V VO = 0 V EN = VI , TJ = 25C EN = VI TPS75901 TPS75915 FB = 1.5 V f = 100 Hz, TJ = 25C, VI = 2.8 V, IO = 7.5 A IO(PG) = 300 A, V(PG) 0.8 V VO decreasing Measured at VO VI = 2.8 V, IO(PG) = 1 mA V(PG) = 5 V EN = VI EN = 0 V -1 -1 2 0.7 0 89 0.5 0.15 0.4 1 1 1 -1 58 0 93 8 35 10 150 0.1 10 1 14 3.201 125 200 0.04 0.1 2.425 3.3 3.399 1.746 2.5 2.575 1.455 1.8 1.854 V V A %/V %/V Vrms A C A A A dB V %VO %VO V A A A V V 0.97 VO 0.98 VO 1.5 1.545 V MIN TYP VO 1.03 VO 1.02 VO V MAX UNIT
1.5 V Output Output voltage (1) 1.8 V Output 2.5 V Output 3.3 V Output Quiescent current (GND current) (3), (4) Output voltage line regulation (VO/VO) (4) Load regulation (3) Output noise voltage Output current limit Thermal shutdown junction temperature Standby current FB input current Power supply ripple rejection PG trip threshold voltage PGhysteresis voltage PGoutput low voltage PG leakage current Input current (EN) High level EN input voltage Low level EN input voltage (1) (2) (3) (4)
Minimum input voltage for valid PG Fixed options only Fixed options only Fixed options only Fixed options only
IO = 0 mA to 7.5 A The adjustable option operates with a 2% tolerance over TJ = 0 to 125C. IO = 0 mA to 7.5 A If VO 1.8 V then VImin = 2.8 V, VImax = 5.5 V: VO VImax * 2.8V Line regulator (mV) + (%V) 1000 100 If VO 2.5 V then VImin = VO + 1 V, VImax = 5.5 V: VO VImax * VO ) 1V Line regulator (mV) + (%V) 1000 100
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SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range (TJ = -40C to 125C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 100 F (unless otherwise noted)
PARAMETER VO Dropout voltage (3.3 V output) (5) TEST CONDITIONS IO = 7.5 A, VI = 3.2 V, TJ = 25C IO = 7.5 A, VI = 3.2 V 10 2.2 100 25 2.75 TJ = 25C, VI rising TJ = 25C, VI falling MIN TYP 400 750 MAX UNIT mV mV mA V mV
Discharge transistor current VO = 1.5 V, TJ = 25C VI UVLO UVLO hysteresis
(5)
IN voltage equals VO(Typ) - 100 mV; TPS75915, TPS75918, and TPS75925 dropout voltage limited by input voltage range limitations (i.e., TPS75933 input voltage is set to 3.2 V for the purpose of this test).
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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TYPICAL CHARACTERISTICS Table of Graphs
FIGURE VO Output voltage Ground current Power supply ripple rejection Output spectral noise density zo VDO VI Output impedance Dropout voltage Minimum required input voltage Line transient response Load transient response VO Output voltage and enable voltage Equivalent series resistance (ESR) vs Time (start-up) vs Output current vs Output current vs Junction temperature vs Junction temperature vs Frequency vs Frequency vs Frequency vs Input voltage vs Junction temperature vs Output voltage 2, 3 4, 5 6 7 8 9 10 11 12 13, 15 14, 16 17 19, 20
TPS75933 OUTPUT VOLTAGE vs OUTPUT CURRENT
3.345 VI = 4.3 V TJ = 25C 3.330 VO - Output Voltage - V VO - Output Voltage - V 1.530 1.545 VI = 2.8 V TJ = 25C
TPS75915 OUTPUT VOLTAGE vs OUTPUT CURRENT
3.315
1.515
3.3
1.5
3.285
1.485
3.270
1.470
3.255 0 1.5 3 4.5 6 7.5 IO - Output Current - A
1.455
0
1.5
3
4.5
6
7.5
IO - Output Current - A
Figure 2.
Figure 3.
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
TPS75933 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE
3.345 VI = 4.3 V 3.33 VO - Output Voltage - V VO - Output Voltage - V 1.530 1.545 VI = 2.8 V
TPS75915 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE
3.315
1.515
3.3
1.5
3.285
1.485
3.270
1.470
3.255 -40 -25
10
5
20
35
50
65 80
95 110 125
1.455 -40 -25 -10
5
20
35
50 65
80
95 110 125
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 4. TPS759xx GROUND CURRENT vs JUNCTION TEMPERATURE
118 PSRR - Power Supply Ripple Rejection - dB 116 114 Ground Current - A 112 110 108 106 104 102 -40 -25 -10 VI = 5 V IO = 7.5 A 90 80 70 60 50 40 30 20 10 0 10 100 1k IO = 7.5 A VI = 4.3 V Co = 100 F TJ = 25C
Figure 5. TPS75933 POWER SUPPLY RIPPLE REJECTION vs FREQUENCY
IO = 1 mA
5
20
35 50
65
80
95 110 125
10k
100k
1M
10M
TJ - Junction Temperature - C
f - Frequency - Hz
Figure 6.
Figure 7.
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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TYPICAL CHARACTERISTICS (continued)
TPS75933 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
2.5 Hz VI = 4.3 V VO = 3.3 V Co = 100 F TJ = 25C IO = 7.5 A 1.5 IO = 1 mA 1 100 10 z o - Output Impedance - 1 0.1 0.01 IO = 7.5 A VI = 4.3 V Co = 100 F TJ = 25C IO = 1 mA
TPS75933 OUTPUT IMPEDANCE vs FREQUENCY
Output Spectral Noise Density - V/
2
0.001
0.5 0.0001 0 10 0.00001 10
100
1k f - Frequency - Hz
10k
100k
100
1k 10k 100k f - Frequency - Hz
1M
10M
Figure 8. TPS75901 DROPOUT VOLTAGE vs INPUT VOLTAGE
700 IO = 7.5 A 600 VDO - Dropout Voltage - mV 500 400 TJ = 25C 300 TJ = -40C 200 100 0 2.5 3 3.5 4 VI - Input Voltage - V 4.5 5 TJ = 125C VDO - Dropout Voltage - mV 500 600 IO = 7.5 A
Figure 9. TPS75933 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
400
300
200
100
0 -40 -25 -10 -5
20 35
50 65
80 95 110 125
TJ - Junction Temperature - C
Figure 10.
Figure 11.
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE
VO - Change in Output Voltage - mV
TPS75915 LINE TRANSIENT RESPONSE
VO = 1.5 V IO = 7.5 A Co = 100 F
4 IO = 7.5 A VI- Minimum Required Input Voltage - V TJ = 125C TJ = 25C TJ = -40C 3 2.8
50 0 -50
-100 VI - Input Voltage - V VI - Input Voltage - V
3.7 2.8
2 1.5
1.75
2
3 2.25 2.5 2.75 VO - Output Voltage - V
3.25
3.5
0
50
100 150 200 250 300 350 400 450 500 t - Time - s
Figure 12.
Figure 13.
TPS75915 LOAD TRANSIENT RESPONSE
VO - Change in Output Voltage - mV VO = 1.5 V Co = 100 F VO - Change in Output Voltage - mV 200 100 0 -100 -200 10 5 0 I O - Output Current - A di + 1 A ms dt
TPS75933 LINE TRANSIENT RESPONSE
VO = 3.3 V IO = 7.5 A Co = 100 F
50
0 -50
-100
5.3 4.3
0
20
40
60
80 100 120 140 160 180 200 t - Time - s
0
50
100 150 200 250 300 350 400 450 500 t - Time - s
Figure 14.
Figure 15.
11
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SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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TYPICAL CHARACTERISTICS (continued)
TPS75933 OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP)
VO - Output Voltage - V VI = 4.3 V IO = 10 mA TJ = 25C
TPS75933 LOAD TRANSIENT RESPONSE
VO - Change in Output Voltage - mV 200 100 0 -100 -200 I O - Output Current - A 10 7.5 5 0 di + 1 A ms dt VO = 3.3 V Co = 100 F
3.3
0 4.3 0
0
20
40
60
80 100 120 140 160 180 200 t - Time - s
Enable Voltage - V
0
0.2
0.4 0.6 t - Time (Start-Up) - ms
0.8
1
Figure 16.
Figure 17.
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SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
VI IN OUT + EN Co GND ESR RL To Load
Figure 18. Test Circuit for Typical Regions of Stability (See Figure 19 and Figure 20) (Fixed Output Options)
TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(A) vs OUTPUT CURRENT
10 ESR - Equivalent Series Resistance - Co = 680 F TJ = 25C 10 ESR - Equivalent Series Resistance - Co = 47 F TJ = 25C
TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(A) vs OUTPUT CURRENT
1 Region of Stability
1 Region of Stability
0.2
0.1
Region of Instability
0.015 Region of Instability 0.01 0 1.5 3 4.5 6 7.5 IO - Output Current - A 0.01 0 1.5 3 4.5 6 7.5 IO - Output Current - A
Figure 19.
Figure 20.
A. Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, ay series resistance added externally, and PWB trace resistance to CO.
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THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
P max + V *V D I(avg) O(avg) I O(avg) )V I(avg) xI (Q)
(1)
Where:
* * * * VI(avg) is the average input voltage. VO(avg) is the average output voltage. IO(avg) is the average output current. I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RJC), the case to heatsink (RCS), and the heatsink to ambient (RSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance. Figure 21 illustrates these thermal resistances for (a) a TO-220 package attached to a heatsink, and (b) a TO-263 package mounted on a JEDEC High-K board.
C B A A RJC B RCS C RSA C TC TJ A B
TA TO-220 Package (a)
TO-263 Package (b)
Figure 21. Thermal Resistances
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THERMAL INFORMATION (continued)
Equation 2 summarizes the computation:
T J + T ) PDmax x R )R )R A JC CS SA
(2)
The RJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator's data sheet. The RSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks, like the one attached to the TO-220 package in Figure 21(a), can have RCS values ranging from 5C/W for very large heatsinks to 50C/W for very small heatsinks. The RCSis a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a TO-220 package, RCSof 1C/W is reasonable. Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted will provide some heatsinking through the pin solder connections. Some packages, like the TO-263 and TI's TSSOP PowerPADTM packages, use a copper plane underneath the package or the circuit board's ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RJA). This RJA is valid only for the specific operating environment used in the computer model. Equation 2 simplifies into Equation 3: T + T ) PDmax x R J A JA Rearranging Equation 3 gives Equation 4: T -T R +JA JA P max
D
(3)
(4)
Using Equation 3 and the computer model generated curves shown in Figure 22 and Figure 25, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment.
TO-220 POWER DISSIPATION
The TO-220 package provides an effective means of managing power dissipation in through-hole applications. The TO-220 package dimensions are provided in the Mechanical Data section at the end of the data sheet. A heatsink can be used with the TO-220 package to effectively lower the junction-to-ambient thermal resistance. To illustrate, the TPS75925 in a TO-220 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P Dmax + (3.3 - 2.5) V x 3 A + 2.4 W (5) Substituting TJmax for TJ into Equation 4 gives Equation 6: R max + (125 - 55) C 2.4 W + 29 C W JA
(6)
From Figure 22, RJA vs Heatsink Thermal Resistance, a heatsink with RSA = 22C/W is required to dissipate 2.4 W. The model operating environment used in the computer model to construct Figure 22 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Since the package pins were soldered to the board, 450 mm2 of the board was modeled as a heatsink. Figure 23 shows the side view of the operating environment used in the computer model.
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THERMAL INFORMATION (continued)
65 Natural Convection
C/W
55 Air Flow = 150 LFM 45 Air Flow = 250 LFM Air Flow = 500 LFM 35
R JA - Thermal Resistance -
25
15 No Heatsink 5 25 20 15 10 5 RSA - Heatsink Thermal Resistance - C/W 0
Figure 22. Thermal Resistance vs Heatsink Thermal Resistance
0.21 mm
0.21 mm
1 oz. Copper Ground Plane
1 oz. Copper Power Plane
Figure 23. From the data in Figure 22 and rearranging Equation 4, the maximum power dissipation for a different heatsink RSA and a specific ambient temperature can be computed (see Figure 24).
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THERMAL INFORMATION (continued)
10 TA = 55C PD - Power Dissipation Limit - W Air Flow = 500 LFM Air Flow = 250 LFM Air Flow = 150 LFM
Natural Convection No Heatsink 1 20 10 RSA - Heatsink Thermal Resistance - C/W 0
Figure 24. Power Dissipation vs Heatsink Thermal Resistance The TO-263 package provides an effective means of managing power dissipation in surface mount applications. The TO-263 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the TO-263 package enhances the thermal performance of the package. To illustrate, the TPS75925 in a TO-263 package was chosen. For this example, the average input voltage is 3.3V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P Dmax + (3.3 - 2.5) V x 3 A + 2.4 W (7) Substituting TJmax for TJ into Equation 4 gives Equation 8: R max + (125 - 55) C 2.4 W + 29 C W JA
2
(8)
From Figure 25, RJA vs Copper Heatsink Area, the ground plane needs to be 2 cm for the part to dissipate 2.4W. The model operating environment used in the computer model to construct Figure 25 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows the side view of the operating environment used in the computer model.
17
TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
www.ti.com
THERMAL INFORMATION (continued)
40 No Air Flow
C/W
R JA - Thermal Resistance -
35 150 LFM 30 250 LFM 25
20
15 0
0.01 0.1 1 10 Copper Heatsink Area - cm2
100
Figure 25. Thermal Resistance vs Copper Heatsink Area
2 oz. Copper Solder Pad with 25 Thermal Vias
1 oz. Copper Power Plane
1 oz. Copper Ground Plane
Thermal Vias, 0.3 mm Diameter, 1.5 mm Pitch
Figure 26. From the data in Figure 25 and rearranging Equation 4, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (see Figure 27).
18
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
THERMAL INFORMATION (continued)
5 TA = 55C PD - Maximum Power Dissipation - W
4
250 LFM
150 LFM 3
No Air Flow 2
1 0 0.01 0.1 1 10 Copper Heatsink Area - cm2 100
Figure 27. Maximum Power Dissipation vs Copper Heatsink Area
19
TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
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APPLICATION INFORMATION PROGRAMMING THE TPS75901 ADJUSTABLE LDO REGULATOR
The output voltage of the TPS75901 adjustable regulator is programmed using an external resistor divider as shown in Figure 28. The output voltage is calculated using:
V Where: Vref = 1.224 V typ (the internal reference voltage)
(9)
O
+V
ref
1 ) R1 R2
Resistors R1 and R2 should be chosen for approximately 40-A divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 40 A and then calculate R1 using:
V R1 + V O *1 ref R2
(10)
TPS75901 VI 2V 0.7 V EN OUT R1 FB GND R2 VO Co IN OUTPUT VOLTAGE 2.5 V 3.3 V 3.6 V R1 31.6 51 58.3 R2 30.1 30.1 30.1 UNIT k k k OUTPUT VOLTAGE PROGRAMMING GUIDE
1 F
Figure 28. TPS75901 Adjustable LDO Regulator Programming
REGULATOR PROTECTION
The TPS759xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS759xx also features internal current limiting and thermal protection. During normal operation, the TPS759xx limits output current to approximately 10 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130C (typ), regulator operation resumes.
INPUT CAPACITOR
For a typical application, a ceramic input bypass capacitor (0.22 F-1 F) is recommended to ensure device stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply, large transient currents will cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO threshold, the device will turn off. Therefore, it is recommended that a larger capacitor be placed in parallel with the ceramic bypass capacitor at the regulator's input. The size of this capacitor depends on the output current, response time of the main power supply, and the main power supply's distance to the regulator. At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum UVLO threshold voltage during normal operating conditions.
20
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TPS75901, TPS75915 TPS75918, TPS75925, TPS75933
SLVS318E - DECEMBER 2000 - REVISED MARCH 2004
APPLICATION INFORMATION (continued) OUTPUT CAPACITOR
As with most LDO regulators, the TPS759xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 F with an ESR (equivalent series resistance) of at least 200 m. As shown in Figure 29, most capacitor and ESR combinations with a product of 47e-6 x 0.2 = 9.4e-6 or larger will be stable, provided the capacitor value is at least 47 F. Solid tantalum electrolytic and aluminum electrolytic capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors provide a wider range of stability and better load transient response. This information along with the ESR graphs, Figure 19, Figure 20, and Figure 29, is included to assist in selection of suitable capacitance for the user's application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines.
1000 Region of Stability Output Capacitance - F
ESR min x Co = Constant 100
47
Region of Instability Y = ESRmin x Co 10 0.01 0.1 ESR - Equivalent Series Resistance - 0.2
Figure 29. Output Capacitance vs Equivalent Series Resistance
21
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device TPS75901KC TPS75901KTT TPS75901KTTR TPS75901KTTT TPS75915KC TPS75915KTT TPS75915KTTR TPS75915KTTT TPS75918KC TPS75918KTT TPS75918KTTR TPS75918KTTT TPS75925KC TPS75925KTT TPS75925KTTR TPS75925KTTT TPS75933KC TPS75933KTT TPS75933KTTR TPS75933KTTT
(1)
Status (1) ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE
Package Type TO-220 DDPAK/ TO-263 DDPAK/ TO-263 DDPAK/ TO-263 TO-220 DDPAK/ TO-263 DDPAK/ TO-263 DDPAK/ TO-263 TO-220 DDPAK/ TO-263 DDPAK/ TO-263 DDPAK/ TO-263 TO-220 DDPAK/ TO-263 DDPAK/ TO-263 DDPAK/ TO-263 TO-220 DDPAK/ TO-263 DDPAK/ TO-263 DDPAK/ TO-263
Package Drawing KC KTT KTT KTT KC KTT KTT KTT KC KTT KTT KTT KC KTT KTT KTT KC KTT KTT KTT
Pins Package Eco Plan (2) Qty 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 500 50 500 50 50 500 50 50 500 50 50 500 50 50 50 None None None None None None None None None None None None None None None None None None None None
Lead/Ball Finish CU SN Call TI CU SN CU SN CU SN Call TI CU SN CU SN CU SN Call TI CU SN CU SN CU SN Call TI CU SN CU SN CU SN Call TI CU SN CU SN
MSL Peak Temp (3) Level-NA-NA-NA Call TI Level-2-220C-1 YEAR Level-2-220C-1 YEAR Level-NA-NA-NA Call TI Level-2-220C-1 YEAR Level-2-220C-1 YEAR Level-NA-NA-NA Call TI Level-2-220C-1 YEAR Level-2-220C-1 YEAR Level-NA-NA-NA Call TI Level-2-220C-1 YEAR Level-2-220C-1 YEAR Level-NA-NA-NA Call TI Level-2-220C-1 YEAR Level-2-220C-1 YEAR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSOT008B - JANUARY 1995 - REVISED SEPTEMBER 2000
KC (R-PSFM-T5)
0.420 (10,67) 0.380 (9,65) 0.113 (2,87) 0.103 (2,62) 0.185 (4,70) 0.175 (4,46)
PLASTIC FLANGE-MOUNT
0.156 (3,96) DIA 0.146 (3,71)
0.055 (1,40) 0.045 (1,14)
0.147 (3,73) 0.137 (3,48) 0.340 (8,64) 0.330 (8,38)
0.125 (3,18) (see Note C)
1.037 (26,34) 0.997 (25,32)
1 0.040 (1,02) 0.030 (0,76) 0.010 (0,25) M
5 0.122 (3,10) 0.102 (2,59) 0.025 (0,64) 0.012 (0,30) 4040208/E 09/00
0.067 (1,70) 0.268 (6,81)
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Lead dimensions are not controlled within this area. All lead dimensions apply before solder dip. The center lead is in electrical contact with the mounting tab.
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* DALLAS, TEXAS 75265
1
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